1. Field of the Invention
The present invention relates to a memory device having off-chip drivers that include an enable circuit and related methods for reducing delays during read operations of the memory device.
2. Description of the Related Art
Attempts to minimize size and power consumption of electronic memory devices, such as dynamic random access memories (DRAMs), often lead to omitting certain components and features that may otherwise enhance memory device operation. Such considerations may be particularly important in applications where the memory device is incorporated into a battery-powered or mobile device. For example, some specialty memory devices, such as those used in mobile applications, may not feature any on-chip delay locked loops (DLLs), which are useful for aligning clocks and maintaining timing precision but tend to consume considerable power. Such a memory device can be, for example, a double data rate synchronous dynamic random access memory (DDR SDRAM), which is capable of reading out stored data in read bursts. With each read command, a read burst operation sequentially transmits a given number of data words from the memory device to the system in which the memory device is operating. A DDR SDRAM chip facilitates data transfers on both edges of each successive clock cycle (i.e., both the rising and falling edges), thereby doubling the memory chip data throughput. The data, conventionally denoted as “DQ,” is driven off the chip via off-chip drivers (OCD).
Normally, an on-chip DLL aligns the read output to the external system clock (VCLK). Where the on-chip DLL is omitted for size or power considerations, any propagation delay of the internal clocking tree and logic after the last clocked stage before the output pad of the memory device data adds to the output delay (tAC) measured from the rising edge of VCLK. More specifically, the internal clock tree essentially derives various clock signals from the external VCLK signal, which are used to time a variety of operations on the memory device. However, the process of generating these internal clock signals and propagation delays across the chip result in timing offsets between the external VCLK signal and the various internal clock signals. Further, any logic circuitry that exists between the point of application of the internal clock signal and the output terminal contributes to the output delay tAC between the VCLK signal and the arrival of data at the output.
While some degree of output delay time tAC is acceptable, it is desirable to minimize the variability of tAC, such that the timing of data driven off memory chips is predictable and consistent from OCD to OCD, from chip to chip, and for each individual OCD over the operating time period of the system containing the memory devices, such that the variation of tAC remains within acceptable operational tolerances. Reducing the number of different delays that contribute to tAC tends to reduce the overall variability of tAC.
Moreover, the overall delay in retrieving stored data in response to a read command must be taken into consideration when designing memory devices. This timing “budget” may include a number of factors, including tAC. Thus, in general, reducing the value of tAC can either reduce the overall delay in retrieving data or can permit other delays that contribute to the overall delay to be increased without exceeding the overall timing budget. Further, reducing the value of tAC may permit greater timing flexibility in latching retrieved data at the OCDs, thereby providing greater leeway in the timing of the clock signal used to supply the data to the OCDs.